Improving Network-on-Chip-based turbo decoder architectures

TL;DR

This paper enhances Network-on-Chip turbo decoder architectures by increasing throughput with adaptive techniques and reducing area for double-binary decoders through novel data representation methods, achieving significant improvements in speed and size.

Contribution

It introduces adaptive-bandwidth reduction for throughput gains and novel data representations to lower area in double-binary turbo decoders.

Findings

Over 60 Mb/s throughput improvement with adaptive bandwidth reduction

Area reduction of over 40% for double-binary decoders

Performance degradation of about 0.2 dB with new techniques

Abstract

In this work novel results concerning Network-on-Chip-based turbo decoder architectures are presented. Stemming from previous publications, this work concentrates first on improving the throughput by exploiting adaptive-bandwidth reduction techniques. This technique shows in the best case an improvement of more than 60 Mb/s. Moreover, it is known that double-binary turbo decoders require higher area than binary ones. This characteristic has the negative effect of increasing the data width of the network nodes. Thus, the second contribution of this work is to reduce the network complexity to support doublebinary codes, by exploiting bit-level and pseudo-floating-point representation of the extrinsic information. These two techniques allow for an area reduction of up to more than the 40% with a performance degradation of about 0.2 dB.