Ge quantum dot arrays grown by ultrahigh vacuum molecular beam epitaxy on the Si(001) surface: nucleation, morphology and CMOS compatibility

TL;DR

This paper investigates the nucleation, morphology, and growth of Ge quantum dot arrays on Si(001) surfaces via ultrahigh vacuum molecular beam epitaxy, focusing on temperature effects and CMOS-compatible low-temperature processes.

Contribution

It proposes atomic models for Ge hut growth, explores low-temperature array formation, and suggests hydrogenation to reduce pre-growth cleaning temperature for CMOS compatibility.

Findings

Different nucleation mechanisms at <600°C and >600°C.

Atomic models for pyramids and wedges of Ge huts.

Hydrogenation reduces Si surface cleaning temperature.

Abstract

Issues of morphology, nucleation and growth of Ge cluster arrays deposited by ultrahigh vacuum molecular beam epitaxy on the Si(001) surface are considered. Difference in nucleation of quantum dots during Ge deposition at low (<600 deg C) and high (>600 deg. C) temperatures is studied by high resolution scanning tunneling microscopy. The atomic models of growth of both species of Ge huts---pyramids and wedges---are proposed. The growth cycle of Ge QD arrays at low temperatures is explored. A problem of lowering of the array formation temperature is discussed with the focus on CMOS compatibility of the entire process; a special attention is paid upon approaches to reduction of treatment temperature during the Si(001) surface pre-growth cleaning, which is at once a key and the highest-temperature phase of the Ge/Si(001) quantum dot dense array formation process. The temperature of the Si clean surface preparation, the final high-temperature step of which is, as a rule, carried out directly in the MBE chamber just before the structure deposition, determines the compatibility of formation process of Ge-QD-array based devices with the CMOS manufacturing cycle. Silicon surface hydrogenation at the final stage of its wet chemical etching during the preliminary cleaning is proposed as a possible way of efficient reduction of the Si wafer pre-growth annealing temperature.