Operand Folding Hardware Multipliers

TL;DR

This paper introduces a novel accumulate-and-add multiplication algorithm that partitions operands to achieve a more compact and faster hardware multiplier, significantly reducing the number of additions needed for large bit-lengths.

Contribution

The paper presents a new operand partitioning method for accumulate-and-add multiplication, reducing addition count and improving hardware efficiency for large operands.

Findings

Requires only 0.194m+56 additions for 1024-bit operands

Approximately halves the additions compared to classical methods

Results in more compact and faster hardware multipliers

Abstract

This paper describes a new accumulate-and-add multiplication algorithm. The method partitions one of the operands and re-combines the results of computations done with each of the partitions. The resulting design turns-out to be both compact and fast. When the operands' bit-length $m$ is 1024, the new algorithm requires only $0.194m+56$ additions (on average), this is about half the number of additions required by the classical accumulate-and-add multiplication algorithm ($\frac{m}2$).