Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET

TL;DR

This paper explores the scalability of spin FPGA architectures using spin MOSFET technology, demonstrating potential advantages in area reduction and speed increase over traditional CMOS FPGAs across multiple process nodes.

Contribution

It introduces a reconfigurable spin FPGA architecture with high magnetocurrent ratios and benchmarks its performance against CMOS FPGA, highlighting scalability benefits.

Findings

Spin FPGA shows reduced area compared to CMOS FPGA.

Spin FPGA achieves higher speed performance.

Scalability demonstrated across 22nm, 32nm, and 45nm technologies.

Abstract

Scalability of Field Programmable Gate Array (FPGA) using spin MOSFET (spin FPGA) with magnetocurrent (MC) ratio in the range of 100% to 1000% is discussed for the first time. Area and speed of million-gate spin FPGA are numerically benchmarked with CMOS FPGA for 22nm, 32nm and 45nm technologies including 20% transistor size variation. We show that area is reduced and speed is increased in spin FPGA owing to the nonvolatile memory function of spin MOSFET.