ReveR: Software Simulator of Reversible Processor with Stack
Alexander Yu. Vlasov
TL;DR
This paper presents ReveR, a software simulation of a reversible processor with stack support, detailing its architecture, elementary operations, control flow, and procedure calls in assembler language.
Contribution
It introduces a comprehensive software model of a reversible processor with stack functionality, including architecture and implementation details.
Findings
Successfully implemented a reversible processor model
Demonstrated control flow and procedure call mechanisms
Provided a foundation for reversible computing simulations
Abstract
A software model of a reversible processor ReveR with the stack is discussed in this paper. An architecture, the minimal set of elementary reversible operations together with an implementation of the basic control flow structures and procedures calls using simple assembler language are described.
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Taxonomy
TopicsComputability, Logic, AI Algorithms · Quantum Computing Algorithms and Architecture · Parallel Computing and Optimization Techniques