Substrate Gating of Contact Resistance in Graphene Transistors

TL;DR

This paper investigates how substrate gating influences contact resistance in graphene transistors, revealing that interface engineering can significantly improve device performance by modulating electrostatics at the contact interface.

Contribution

It introduces a model explaining contact resistance modulation via substrate gating and highlights the importance of interface engineering for graphene transistor optimization.

Findings

Effective interfacial dielectric layer impacts contact resistance.

Quantum transport calculations match experimental data.

Substrate gating can modulate electron-hole conductance asymmetry.

Abstract

Metal contacts have been identified to be a key technological bottleneck for the realization of viable graphene electronics. Recently, it was observed that for structures that possess both a top and a bottom gate, the electron-hole conductance asymmetry can be modulated by the bottom gate. In this letter, we explain this observation by postulating the presence of an effective thin interfacial dielectric layer between the metal contact and the underlying graphene. Electrical results from quantum transport calculations accounting for this modified electrostatics corroborate well with the experimentally measured contact resistances. Our study indicates that the engineering of metal- graphene interface is a crucial step towards reducing the contact resistance for high performance graphene transistors.