Power Consumption of LDPC Decoders in Software Radio

TL;DR

This paper evaluates the complexity and power consumption of LDPC decoders on general purpose processors in software radio, proposing power control schemes to optimize energy efficiency in communication systems.

Contribution

It provides the first estimation and comparison of LDPC decoding algorithms' power use on processors and introduces two novel power management strategies for software radio.

Findings

LDPC decoding algorithms vary significantly in power consumption.

Proposed power control schemes can effectively reduce energy use.

Analysis aids in designing energy-efficient software radio systems.

Abstract

LDPC code is a powerful error correcting code and has been applied to many advanced communication systems. The prosperity of software radio has motivated us to investigate the implementation of LDPC decoders on processors. In this paper, we estimate and compare complexity and power consumption of LDPC decoding algorithms running on general purpose processors. Using the estimation results, we show two power control schemes for software radio: SNR-based algorithm diversity and joint transmit power and receiver energy management. Overall, this paper discusses general concerns about using processors as the software radio platform for the implementation of LDPC decoders.