Experimental Evidence of Ferroelectric Negative Capacitance in Nanoscale Heterostructures

TL;DR

This paper demonstrates negative capacitance in nanoscale ferroelectric-dielectric heterostructures, showing potential for lowering subthreshold slope in transistors, with experimental and theoretical support.

Contribution

It provides the first proof-of-concept experimental evidence of negative capacitance in nanoscale ferroelectric heterostructures, supported by theoretical calculations.

Findings

Capacitance of heterostructure exceeds that of dielectric alone

Temperature effectively tunes negative capacitance effect

Theoretical models qualitatively agree with experimental results

Abstract

We report a proof-of-concept demonstration of negative capacitance effect in a nanoscale ferroelectric-dielectric heterostructure. In a bilayer of ferroelectric, Pb(Zr0.2Ti0.8)O3 and dielectric, SrTiO3, the composite capacitance was observed to be larger than the constituent SrTiO3 capacitance, indicating an effective negative capacitance of the constituent Pb(Zr0.2Ti0.8)O3 layer. Temperature is shown to be an effective tuning parameter for the ferroelectric negative capacitance and the degree of capacitance enhancement in the heterostructure. Landau's mean field theory based calculations show qualitative agreement with observed effects. This work underpins the possibility that by replacing gate oxides by ferroelectrics in MOSFETs, the sub threshold slope can be lowered below the classical limit (60 mV/decade).