Lattice QCD Applications on QPACE

TL;DR

This paper discusses the design and implementation of QPACE, a high-performance computing architecture optimized for lattice QCD simulations, highlighting strategies for porting applications and performance results.

Contribution

It introduces QPACE, a novel massively parallel architecture with a custom FPGA network and strategies for efficient application porting and performance optimization.

Findings

QPACE achieves high performance for lattice QCD applications.

Effective porting strategies improve application efficiency.

Performance benchmarks demonstrate scalability and speed.

Abstract

QPACE is a novel massively parallel architecture optimized for lattice QCD simulations. A single QPACE node is based on the IBM PowerXCell 8i processor. The nodes are interconnected by a custom 3-dimensional torus network implemented on an FPGA. The compute power of the processor is provided by 8 Synergistic Processing Units. Making efficient use of these accelerator cores in scientific applications is challenging. In this paper we describe our strategies for porting applications to the QPACE architecture and report on performance numbers.