Decimation-Enhanced Finite Alphabet Iterative Decoders for LDPC codes on the BSC

TL;DR

This paper introduces decimation-enhanced finite alphabet iterative decoders for LDPC codes on the BSC, improving error correction speed and analysis simplicity while maintaining high performance in the error floor region.

Contribution

It proposes a decimation technique integrated into FAID decoders, reducing iterations needed for error correction and facilitating analysis for LDPC codes on the BSC.

Findings

Decimation reduces the number of iterations for fixed error correction.

The scheme maintains performance in the error floor region.

Provides insights into decoder analysis and conditions for optimal performance.

Abstract

Finite alphabet iterative decoders (FAID) with multilevel messages that can surpass BP in the error floor region for LDPC codes on the BSC were previously proposed. In this paper, we propose decimation-enhanced decoders. The technique of decimation which is incorporated into the message update rule, involves fixing certain bits of the code to a particular value. Under appropriately chosen rules, decimation can significantly reduce the number of iterations required to correct a fixed number of errors, while maintaining the good performance of the original decoder in the error floor region. At the same time, the algorithm is much more amenable to analysis. We shall provide a simple decimation scheme for a particularly good 7-level FAID for column-weight three codes on the BSC, that helps to correct a fixed number of errors in fewer iterations, and provide insights into the analysis of the decoder. We shall also examine the conditions under which the decimation-enhanced 7-level FAID performs at least as good as the 7-level FAID.