Hybrid CMOS-MQCA Logic Architectures using Multi-Layer Spintronic Devices

TL;DR

This paper introduces a hybrid CMOS-MQCA architecture utilizing multi-layer spintronic devices, demonstrating significant energy savings and new approaches for clocking and read-out schemes in nanoscale circuits.

Contribution

It proposes a novel hybrid architecture with a new spintronic device model, enabling circuit simulation and variability-tolerance improvements.

Findings

70% reduction in energy consumption compared to conventional schemes

Feasibility demonstrated with 22nm CMOS technology

New spin transfer torque clocking and read-out approaches

Abstract

We present a novel hybrid CMOS-MQCA architecture using multi-layer Spintronic devices as computing elements. A feasibility study is presented with 22nm CMOS where new approaches for spin transfer torque induced clocking and read-out scheme for variability-tolerance are introduced. A first-of-its-kind Spintronic device model enables circuit simulation using existing CAD infrastructure. Approximately 70% reduction in energy consumption is observed when compared against conventional field-induced clocking scheme.