Underlap Optimization in HFinFET in Presence of Interface Traps

TL;DR

This study uses 3D device simulation to optimize underlap in HFinFET transistors, enhancing performance and mitigating interface trap effects in ultra-short channels, with promising results against industry benchmarks.

Contribution

It introduces an optimized underlap design in HFinFETs that improves device performance and reduces interface trap impact, validated through extensive simulation.

Findings

Optimized underlap improves on-off ratio and subthreshold slope.

Underlap tuning mitigates interface trap effects.

Results outperform industry benchmarks.

Abstract

In this work, using 3D device simulation, we perform an extensive gate to source/drain underlap optimization for the recently proposed hybrid transistor, HFinFET, to show that the underlap lengths can be suitably tuned to improve the on-off ratio as well as the subthreshold characteristics in an ultra-short channel n-type device without significant on performance degradation. We also show that the underlap knob can be tuned to mitigate the device quality degradation in presence of interface traps. The obtained results are shown to be very promising when compared against ITRS 2009 performance projections as well as published state of the art planar and non-planar Silicon MOSFET data of comparable gate lengths using standard benchmarking techniques.