Interface trap density metrology from sub-threshold transport in highly scaled undoped Si n-FinFETs

TL;DR

This paper introduces two new methods for measuring interface trap density in highly scaled undoped Si n-FinFETs using sub-threshold transport data combined with Tight-Binding calculations, enabling in situ analysis of advanced multi-gate FETs.

Contribution

It presents novel, reliable techniques for interface trap density metrology based on experimental and theoretical comparisons of channel parameters in FinFETs.

Findings

Methods are consistent and reliable for Dit measurement.

Volume inversion occurs in thinner FinFETs near threshold.

Enhanced understanding of sub-threshold transport and trap effects.

Abstract

Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical Tight-Binding (TB) calculations, this technique can be used to understand the evolution of source-to-channel barrier height (Eb) and of active channel area (S) with gate bias (Vgs). The quantitative difference between experimental and theoretical values that we observe can be attributed to the interface traps present in these FinFETs. Therefore, based on the difference between measured and calculated values of (i) S and (ii) |dEb/dVgs| (channel to gate coupling), two new methods of interface trap density (Dit) metrology are outlined. These two methods are shown to be very consistent and reliable, thereby opening new ways of analyzing in situ state-of-the-art multi-gate FETs down to the few nm width limit. Furthermore, theoretical investigation of the spatial current density reveal volume inversion in thinner FinFETs near the threshold voltage.