Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits
Himanshu Thapliyal, Nagarajan Ranganathan

TL;DR
This paper introduces a reversible logic-based methodology for concurrent multi-bit error detection in nanocircuits, leveraging the inverse property to regenerate inputs and detect faults without extra garbage outputs.
Contribution
It proposes a novel 'inverse and compare' method for fault detection in reversible logic circuits, enabling garbageless design and application to emerging nanotechnologies.
Findings
Enables detection of multi-bit errors in reversible circuits.
Results in garbageless reversible circuit designs.
Demonstrates applicability to quantum dot cellular automata.
Abstract
Reversible logic has promising applications in emerging nanotechnologies, such as quantum computing, quantum dot cellular automata and optical computing, etc. Faults in reversible logic circuits that result in multi-bit error at the outputs are very tough to detect, and thus in literature, researchers have only addressed the problem of online testing of faults that result single-bit error at the outputs based on parity preserving logic. In this work, we propose a methodology for the concurrent error detection in reversible logic circuits to detect faults that can result in multi-bit error at the outputs. The methodology is based on the inverse property of reversible logic and is termed as 'inverse and compare' method. By using the inverse property of reversible logic, all the inputs can be regenerated at the outputs. Thus, by comparing the original inputs with the regenerated inputs,…
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Taxonomy
TopicsQuantum-Dot Cellular Automata · Advanced Memory and Neural Computing · Advancements in Semiconductor Devices and Circuit Design
