High Speed and Area Efficient 2D DWT Processor based Image Compression" Signal & Image Processing

TL;DR

This paper introduces a high-speed, area-efficient 2D DWT processor for image compression, utilizing pipelined architecture on FPGA to enhance performance and resource utilization.

Contribution

The paper presents a novel pipelined partially serial FPGA-based 2D DWT processor design that improves speed and efficiency for image compression applications.

Findings

Operates at 231 MHz on Spartan 3 FPGA

Achieves 15% speed improvement over previous designs

Consumes 117mW power at 28°C junction temperature

Abstract

This paper presents a high speed and area efficient DWT processor based design for Image Compression applications. In this proposed design, pipelined partially serial architecture has been used to enhance the speed along with optimal utilization and resources available on target FPGA. The proposed model has been designed and simulated using Simulink and System Generator blocks, synthesized with Xilinx Synthesis tool (XST) and implemented on Spartan 2 and 3 based XC2S100-5tq144 and XC3S500E-4fg320 target device. The results show that proposed design can operate at maximum frequency 231 MHz in case of Spartan 3 by consuming power of 117mW at 28 degree/c junction temperature. The result comparison has shown an improvement of 15% in speed.