Interface Trap Density Metrology of state-of-the-art undoped Si n-FinFETs

TL;DR

This paper introduces novel methods for directly measuring interface trap density in advanced undoped Si n-FinFETs, addressing a key industry challenge in device degradation analysis.

Contribution

It provides the first direct estimation techniques for Dit in state-of-the-art FinFETs, moving beyond traditional custom-structure measurements.

Findings

First direct Dit measurement methods for FinFETs

Addresses industry need for accurate device degradation metrics

Enables better understanding of interface states in ultra-scaled devices

Abstract

The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed structures. We present the first set of methods that allow direct estimation of Dit in state-of-the-art FinFETs, addressing a critical industry need.