Equivalence Checking in Embedded Systems Design Verification using PRES+ model

TL;DR

This paper introduces a method to verify equivalence between PRES+ models of embedded systems by translating them into FSMD models and using existing equivalence checking tools, addressing a gap in PRES+ verification.

Contribution

It proposes the first known algorithm for translating PRES+ models to FSMD models for equivalence checking in embedded systems verification.

Findings

Successfully translated PRES+ models to FSMD models

Verified equivalence between models using existing tools

Demonstrated approach on real-world examples

Abstract

In this paper we focus on some aspects related to modeling and formal verification of embedded systems. Many models have been proposed to represent embedded systems. These models encompass a broad range of styles, characteristics, and application domains and include the extensions of finite state machines, data flow graphs, communication processes and Petri nets. In this report, we have used a PRES+ model (Petri net based Representation for Embedded Systems) as an extension of classical Petri net model that captures concurrency, timing behaviour of embedded systems; it allows systems to be representative in different levels of abstraction and improves expressiveness by allowing the token to carry information. Modeling using PRES+, as discussed above, may be convenient for specifying the input behaviour because it supports concurrency. However, there is no equivalence checking method reported in the literature for PRES+ models to the best of our knowledge. In contrast, equivalence checking of FSMD models exist. As a first step, therefore, we seek to devise an algorithm to translate PRES+ models to FSMD models and we seek to hand execute our algorithm on a real life example and we have to translate two versions of PRES+ models to FSMD models. Then using existing equivalence checker we have checked the equivalence between two FSMD models.