A Novel and Highly Efficient AES Implementation Robust against Differential Power Analysis

TL;DR

This paper introduces a new AES implementation that significantly enhances resistance to differential power analysis attacks with minimal hardware overhead, maintaining standard compatibility and high efficiency on FPGA hardware.

Contribution

A novel AES implementation using randomization in composite field arithmetic that improves DPA resistance with only 7% area increase and no frequency loss.

Findings

7% area overhead for enhanced security

Maintains standard compatibility and frequency

Validated on Xilinx Spartan-II FPGA

Abstract

Developed by Paul Kocher, Joshua Jaffe, and Benjamin Jun in 1999, Differential Power Analysis (DPA) represents a unique and powerful cryptanalysis technique. Insight into the encryption and decryption behavior of a cryptographic device can be determined by examining its electrical power signature. This paper describes a novel approach for implementation of the AES algorithm which provides a significantly improved strength against differential power analysis with a minimal additional hardware overhead. Our method is based on randomization in composite field arithmetic which entails an area penalty of only 7% while does not decrease the working frequency, does not alter the algorithm and keeps perfect compatibility with the published standard. The efficiency of the proposed technique was verified by practical results obtained from real implementation on a Xilinx Spartan-II FPGA.