Low Power Reversible Parallel Binary Adder/Subtractor

TL;DR

This paper proposes three designs for a reversible 8-bit parallel binary adder/subtractor, emphasizing energy efficiency and improved performance over existing designs, with Design III being the most efficient.

Contribution

It introduces three novel reversible adder/subtractor designs integrating full adders and subtractors in a single unit, enhancing efficiency and reducing quantum cost.

Findings

Design III outperforms other designs in efficiency

Reduced garbage inputs/outputs in proposed designs

Lower quantum cost achieved with Design III

Abstract

In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.