Fault Tolerant Variable Block Carry Skip Logic (VBCSL) using Parity Preserving Reversible Gates

TL;DR

This paper introduces a novel fault-tolerant variable block carry skip logic design using parity-preserving reversible gates, improving hardware efficiency and fault tolerance for low power digital circuits.

Contribution

It proposes a new fault-tolerant design of carry skip adders with variable block logic using parity-preserving reversible gates, optimized for hardware complexity and fault resilience.

Findings

Designs are minimized in hardware complexity and gate count

Proposed designs outperform existing counterparts in fault tolerance

Technology-independent evaluation confirms superiority

Abstract

Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power CMOS design, digital signal processing and nanotechnology. This paper presents the efficient design approaches of fault tolerant carry skip adders (FTCSAs) and compares those designs with the existing ones. Variable block carry skip logic (VBCSL) using the fault tolerant full adders (FTFAs) has also been developed. The designs are minimized in terms of hardware complexity, gate count, constant inputs and garbage outputs. Besides of it, technology independent evaluation of the proposed designs clearly demonstrates its superiority with the existing counterparts.