On the Design and Analysis of Quaternary Serial and Parallel Adders

TL;DR

This paper explores the design and analysis of quaternary adders, introducing equations for full adders, parallel adders with carry look-ahead, and a logarithmic stage adder, culminating in a hybrid design combining serial and parallel benefits.

Contribution

It provides the first comprehensive equations for quaternary adders and proposes a novel hybrid adder design that optimizes speed and area.

Findings

Logarithmic stage adder computes carries in log2(n) time

Hybrid adder combines serial and parallel advantages

Design equations enable efficient quaternary adder implementation

Abstract

Optimization techniques for decreasing the time and area of adder circuits have been extensively studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We develop the equations for single-stage parallel adder which works as a carry look-ahead adder. We also provide the design of a logarithmic stage parallel adder which can compute the carries within log2(n) time delay for n qudits. At last, we compare the designs and finally propose a hybrid adder which combines the advantages of serial and parallel adder.