Power optimized programmable embedded controller

TL;DR

This paper presents a power-optimized programmable embedded controller using clock gating on a RISC-based design, achieving a 33.33% reduction in power consumption on FPGA.

Contribution

It introduces a clock gating technique applied to a fully programmable RISC-based embedded controller, demonstrating significant power savings.

Findings

Power consumption reduced by 33.33% using clock gating.

Design supports smart instruction set, I/O, UART, and variable clock frequencies.

Implementation on FPGA validates the power optimization approach.

Abstract

Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functionality. Clock-gating is the most common technique used for reducing processor's power. In this work clock gating technique is applied to optimize the power of fully programmable Embedded Controller (PEC) employing RISC architecture. The CPU designed supports i) smart instruction set, ii) I/O port, UART iii) on-chip clocking to provide a range of frequencies , iv) RISC as well as controller concepts. The whole design is captured using VHDL and is implemented on FPGA chip using Xilinx .The architecture and clock gating technique together is found to reduce the power consumption by 33.33% of total power consumed by this chip.