Wrapper/TAM Co-Optimization and constrained Test Scheduling for SOCs Using Rectangle Bin Packing
Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Muhammad Rezaul Karim,, Abdullah Al Mahmud, Md. Saiful Islam

TL;DR
This paper presents an integrated framework for SOC test automation that optimizes wrapper and TAM co-optimization using rectangle packing, considering power constraints to improve testing efficiency and safety.
Contribution
It introduces a novel rectangle packing-based approach for wrapper/TAM co-optimization and constrained test scheduling in SOCs, including an efficient wrapper construction algorithm.
Findings
Reduces testing time for cores
Incorporates power constraints into scheduling
Improves SOC test automation efficiency
Abstract
This paper describes an integrated framework for SOC test automation. This framework is based on a new approach for Wrapper/TAM co-optimization based on rectangle packing considering the diagonal length of the rectangles to emphasize on both TAM widths required by a core and its corresponding testing time .In this paper, an efficient algorithm has been proposed to construct wrappers that reduce testing time for cores. Rectangle packing has been used to develop an integrated scheduling algorithm that incorporates power constraints in the test schedule. The test power consumption is important to consider since exceeding the system's power limit might damage the system.
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Taxonomy
TopicsVLSI and Analog Circuit Testing · Integrated Circuits and Semiconductor Failure Analysis · Advancements in Photolithography Techniques
