Synthesis of Fault Tolerant Reversible Logic Circuits

TL;DR

This paper introduces a new parity-preserving reversible logic gate, IG, enabling fault-tolerant circuit synthesis with reduced hardware complexity, applicable in various advanced computing fields.

Contribution

A novel 4x4 universal reversible logic gate, IG, that is parity-preserving and facilitates fault detection, along with a fault-tolerant reversible full adder design using only two IG gates.

Findings

The IG gate can synthesize any Boolean function.

The proposed full adder is more efficient than existing designs.

Fault detection is possible with single signal faults.

Abstract

Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 universal reversible logic gate, IG. It is a parity preserving reversible logic gate, that is, the parity of the inputs matches the parity of the outputs. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. Finally, it is shown how a fault tolerant reversible full adder circuit can be realized using only two IGs. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.