Efficient Wrapper/TAM Co-Optimization for SOC Using Rectangle Packing

TL;DR

This paper introduces an efficient rectangle packing-based algorithm for co-optimizing test wrappers and TAM in SOCs, significantly reducing testing time by balancing TAM width and core testing duration.

Contribution

It presents a novel rectangle packing approach for wrapper/TAM co-optimization that considers both TAM width and testing time to improve SOC testing efficiency.

Findings

Reduces SOC testing time through optimized wrapper/TAM design.

Balances TAM width and testing time effectively.

Provides a new rectangle packing method considering diagonal length.

Abstract

The testing time for a system-on-chip(SOC) largely depends on the design of test wrappers and the test access mechanism(TAM).Wrapper/TAM co-optimization is therefore necessary to minimize SOC testing time . In this paper, we propose an efficient algorithm to construct wrappers that reduce testing time for cores. We further propose a new approach for wrapper/TAM co-optimization based on two-dimensional rectangle packing. This approach considers the diagonal length of the rectangles to emphasize on both TAM widths required by a core and its corresponding testing time.