Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder

TL;DR

This paper introduces a new parity-preserving reversible logic gate, IG, enabling fault-tolerant arithmetic circuits with reduced hardware complexity, useful in low power and quantum computing applications.

Contribution

A novel 4x4 parity-preserving reversible gate (IG) is proposed, facilitating fault-tolerant circuit design with improved efficiency over existing methods.

Findings

Fault-tolerant reversible full adder realized with two IG gates

Proposed design reduces hardware complexity and gate count

Efficient in terms of garbage outputs and constant inputs

Abstract

Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 parity preserving reversible logic gate, IG. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. It is shown that a fault tolerant reversible full adder circuit can be realized using only two IGs. The proposed fault tolerant full adder (FTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.