Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation

TL;DR

This paper develops an analytical model for nanoscale strained-Si/SiGe MOSFETs that accurately predicts output current characteristics, highlighting the impact of strain-induced velocity overshoot for improved analog circuit simulation.

Contribution

It introduces a new analytical model for strained-Si/SiGe MOSFETs that accounts for velocity overshoot effects, enhancing simulation accuracy for nanoscale devices.

Findings

Significant current enhancement due to strain observed in short channel devices.

Model validated against 2D device simulations with high accuracy.

Strain effects improve device performance for analog applications.

Abstract

For nanoscale CMOS applications, strained-silicon devices have been receiving considerable attention owing to their potential for achieving higher performance and compatibility with conventional silicon processing. In this work, an analytical model for the output current characteristics (I-V) of nanoscale bulk strained-Si/SiGe MOSFETs, suitable for analog circuit simulation, is developed. We demonstrate significant current enhancement due to strain, even in short channel devices, attributed to the velocity overshoot effect. The accuracy of the results obtained using our analytical model is verified using two-dimensional device simulations.