Realizing high current gain PNP transistors using a novel Surface Accumulation Layer Transistor (SALTran) concept

TL;DR

This paper introduces a novel PNP Surface Accumulation Layer Transistor (SALTran) on SOI that significantly enhances current gain through surface hole accumulation, validated by detailed simulation comparisons.

Contribution

The paper presents a new SALTran design that achieves approximately 20 times higher current gain than conventional PNP lateral transistors, without sacrificing frequency performance.

Findings

Current gain improved by ~20 times

Surface accumulation of holes enhances performance

No deterioration in cut-off frequency

Abstract

In this paper we report a new PNP Surface Accumulation Layer Transistor (SALTran) on SOI which uses the concept of surface accumulation of holes near the emitter contact to significantly improve the current gain. Using two-dimensional simulation, we have evaluated the performance of the proposed device in detail by comparing its characteristics with those of the previously published conventional PNP lateral bipolar transistor (LBT) structure. From our simulation results it is observed that depending on the choice of the emitter doping and the emitter length, the proposed SALTran exhibits a current gain enhancement of around 20 times that of the compatible lateral bipolar transistor without deteriorating the cut-off frequency. We have discussed the reasons for the improved performance of the SALTran based on our detailed simulation results.