Diminished Short Channel Effects in Nanoscale Double-Gate Silicon-On-Insulator Metal-Oxide- Semiconductor Field-Effect-Transistors due to Induced Back-Gate Step Potential

TL;DR

This paper demonstrates that inducing a step potential at the back gate of an asymmetrical double-gate SOI MOSFET significantly reduces short channel effects in sub-100 nm devices, enhancing device performance.

Contribution

It introduces a novel method of using a back-gate step potential to improve short channel behavior in nanoscale double-gate SOI MOSFETs.

Findings

Reduced short channel effects in sub-100 nm devices

Enhanced control of channel potential profile

Potential for improved device scaling

Abstract

In this letter we discuss how the short channel behavior in sub 100 nm channel range can be improved by inducing a step surface potential profile at the back gate of an asymmetrical double gate (DG) Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor Field-Effect- Transistor (MOSFET) in which the front gate consists of two materials with different work functions.