Compact Modeling of Parasitic Internal Fringe Capacitance Effects on the Threshold Voltage of High-K Gate Dielectric Nanoscale SOI MOSFETs

TL;DR

This paper presents a compact analytical model for parasitic internal fringe capacitance effects on the threshold voltage of high-K dielectric SOI MOSFETs, validated by 2-D simulations.

Contribution

A new compact model that includes parasitic fringe capacitance effects and their impact on threshold voltage in high-K SOI MOSFETs.

Findings

Threshold voltage decreases with increased gate dielectric permittivity.

The model accurately predicts capacitance effects verified by 2-D simulations.

Charge induction from fringe capacitance influences surface potential along the channel.

Abstract

A compact model for the effect of parasitic internal fringe capacitance on threshold voltage in high-K gate dielectric SOI MOSFETs is developed. Our model includes the effects of the gate dielectric permittivity, spacer oxide permittivity, spacer width, gate length and width of MOS structure. A simple expression for parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. We demonstrate an increase in surface potential along the channel due to these charges resulting in a decrease in the threshold voltage with increase in gate dielectric permittivity. The accuracy of the results obtained using our analytical model is verified using 2-D device simulations.