Extended-p+ Stepped Gate (ESG) LDMOS for Improved Performance

TL;DR

This paper introduces an Extended-p+ Stepped Gate (ESG) LDMOS with structural enhancements that significantly improve breakdown voltage, on-resistance, and switching performance based on simulation results.

Contribution

The paper presents a novel ESG LDMOS design with an extended-p+ region and stepped gate structure, achieving notable performance improvements over conventional LDMOS.

Findings

63% increase in breakdown voltage

38% reduction in on-resistance

18% faster switching speed

Abstract

In this paper, we propose a new Extended-p+ Stepped Gate (ESG) thin film SOI LDMOS with an extended-p+ region beneath the source and a stepped gate structure in the drift region of the LDMOS. The hole current generated due to impact ionization is now collected from an n+p+ junction instead of an n+p junction thus delaying the parasitic BJT action. The stepped gate structure enhances RESURF in the drift region, and minimizes the gate-drain capacitance. Based on two-dimensional simulation results, we show that the ESG LDMOS exhibits approximately 63% improvement in breakdown voltage, 38% improvement in on-resistance, 11% improvement in peak transconductance, 18% improvement in switching speed and 63% reduction in gate-drain charge density compared with the conventional LDMOS with a field plate.