Asynchronous logic circuits and sheaf obstructions

TL;DR

This paper introduces a sheaf-based encoding of logic circuits that captures more timing information than static truth tables but less than detailed event-level simulation, bridging static analysis and dynamic behavior.

Contribution

It presents a novel sheaf formalism for logic circuits that reveals additional timing information beyond traditional static analysis.

Findings

Sheaf encoding captures timing behavior of circuits.

More information than static truth tables, less than event simulation.

Provides a new perspective linking static and dynamic circuit analysis.

Abstract

This article exhibits a particular encoding of logic circuits into a sheaf formalism. The central result of this article is that there exists strictly more information available to a circuit designer in this setting than exists in static truth tables, but less than exists in event-level simulation. This information is related to the timing behavior of the logic circuits, and thereby provides a ``bridge'' between static logic analysis and detailed simulation.