Bayesian Post-Processing Methods for Jitter Mitigation in Sampling

TL;DR

This paper introduces a Bayesian stochastic algorithm using Gibbs and slice sampling to improve jitter mitigation in sampling, outperforming traditional linear MMSE and EM-based estimators, thus enabling more efficient ADC designs.

Contribution

It develops a novel Bayesian post-processing algorithm for jitter mitigation that significantly enhances estimation accuracy over existing methods.

Findings

The nonlinear Bayesian algorithm outperforms linear MMSE estimators.

The method improves jitter tolerance, reducing ADC power consumption.

Simulations confirm the effectiveness of the proposed approach.

Abstract

Minimum mean squared error (MMSE) estimators of signals from samples corrupted by jitter (timing noise) and additive noise are nonlinear, even when the signal prior and additive noise have normal distributions. This paper develops a stochastic algorithm based on Gibbs sampling and slice sampling to approximate the optimal MMSE estimator in this Bayesian formulation. Simulations demonstrate that this nonlinear algorithm can improve significantly upon the linear MMSE estimator, as well as the EM algorithm approximation to the maximum likelihood (ML) estimator used in classical estimation. Effective off-chip post-processing to mitigate jitter enables greater jitter to be tolerated, potentially reducing on-chip ADC power consumption.