FPGA Implementation of a Reconfigurable Viterbi Decoder for WiMAX Receiver

TL;DR

This paper presents a low-power, reconfigurable Viterbi decoder implemented on FPGA for WiMAX receivers, enhancing digital communication efficiency with hardware customization.

Contribution

It introduces a novel FPGA-based Viterbi decoder design optimized for low power consumption and reconfigurability in WiMAX applications.

Findings

Successful FPGA implementation on Xilinx Virtex-II Pro

Reduced power consumption compared to traditional decoders

Demonstrated reconfigurability for different WiMAX scenarios

Abstract

Field Programmable Gate Array technology (FPGA) is a highly configurable option for implementing many sophisticated signal processing tasks in Software Defined Radios (SDRs). Those types of radios are realized using highly configurable hardware platforms. Convolutional codes are used in every robust digital communication system and Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. In this paper, a low power-reconfigurable Viterbi decoder for WiMAX receiver is described using a VHDL code for FPGA implementation. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vpx30 FPGA using the FPGA Advantage Pro package provided by Mentor Graphics and ISE 10.1 by Xilinx.