Development of Fast and High Precision CMOS Pixel Sensors for an ILC Vertex Detector

TL;DR

This paper reports on the development of high-speed, high-precision CMOS pixel sensors for the ILC vertex detector, focusing on architecture improvements, device optimization, and future evolution plans to meet stringent specifications.

Contribution

It introduces an evolved CMOS sensor architecture with integrated zero-suppression and column parallel read-out, tailored for different detector layers, advancing towards meeting ILD vertex detector requirements.

Findings

Prototype sensor achieves ~100 μs read-out time

Performance close to ILD specifications

Two device variants optimized for inner and outer layers

Abstract

The development of CMOS pixel sensors with column parallel read-out and integrated zero-suppression has resulted in a full size, nearly 1 Megapixel, prototype with ~100 \mu s read-out time. Its performances are quite close to the ILD vertex detector specifications, showing that the sensor architecture can presumably be evolved to meet these specifications exactly. Starting from the existing architecture and achieved performances, the paper will expose the details of how the sensor will be evolved in the coming 2-3 years in perspective of the ILD Detector Baseline Document, to be delivered in 2012. Two different devices are foreseen for this objective, one being optimized for the inner layers and their fast read-out requirement, while the other exploits the dimmed background in the outer layers to reduce the power consumption. The sensor evolution relies on a high resistivity epitaxial layer, on the use of an advanced CMOS process and on the combination of column-level ADCs with a pixel array. The paper will present how these aspects can be exploited to match the ILD VTX specifications. A status of the development of 3D CMOS devices will be mentioned for completeness.