Model of tunneling transistors based on graphene on SiC

TL;DR

This paper models graphene-on-SiC tunnel FETs, demonstrating their potential for low-power, high-speed nanoelectronics with high on/off ratios and sub-picosecond delays.

Contribution

It provides an accurate model and explores design parameters for graphene-on-SiC TFETs, highlighting their advantages over traditional CMOS devices.

Findings

I_{ON}/I_{OFF} ratios exceeding 10^4 at low voltage

Intrinsic delays smaller than 1 ps

Suitable for low-power, high-speed nanoelectronics

Abstract

Recent experiments shown that graphene epitaxially grown on Silicon Carbide (SiC) can exhibit a energy gap of 0.26 eV, making it a promising material for electronics. With an accurate model, we explore the design parameter space for a fully ballistic graphene-on-SiC Tunnel Field-Effect Transistors (TFETs), and assess the DC and high frequency figures of merit. The steep subthreshold behavior can enable I_{ON}/I_{OFF} ratios exceeding 10^4 even with a low supply voltage of 0.15 V, for devices with gatelength down to 30 nm. Intrinsic transistor delays smaller than 1 ps are obtained. These factors make the device an interesting candidate for low-power nanoelectronics beyond CMOS.