Optimization of reversible sequential circuits

TL;DR

This paper presents optimized reversible sequential circuit designs, including D-latch and JK latch, reducing gate count, delay, and complexity to enhance performance for low power and quantum computing applications.

Contribution

It introduces new reversible latch designs with fewer gates and garbage outputs, improving upon existing literature for low power and quantum computing circuits.

Findings

Reduced number of gates and garbage outputs

Enhanced circuit performance and efficiency

Proposed reversible D-latch and JK latch designs

Abstract

In recent years reversible logic has been considered as an important issue for designing low power digital circuits. It has voluminous applications in the present rising nanotechnology such as DNA computing, Quantum Computing, low power VLSI and quantum dot automata. In this paper we have proposed optimized design of reversible sequential circuits in terms of number of gates, delay and hardware complexity. We have designed the latches with a new reversible gate and reduced the required number of gates, garbage outputs, and delay and hardware complexity. As the number of gates and garbage outputs increase the complexity of reversible circuits, this design will significantly enhance the performance. We have proposed reversible D-latch and JK latch which are better than the existing designs available in literature.