Analysis of Thermoelectric Properties of Scaled Silicon Nanowires Using an Atomistic Tight-Binding Model

TL;DR

This study uses an atomistic tight-binding model to analyze how scaling silicon nanowires affects their thermoelectric properties, revealing potential improvements in ZT at small diameters and discussing design optimization strategies.

Contribution

It introduces an atomistic tight-binding approach combined with the Landauer formalism to evaluate thermoelectric performance of silicon nanowires of various sizes and orientations.

Findings

Scaling nanowires below 7nm can double the power factor and improve ZT.

Orientation and geometry significantly influence thermoelectric performance.

Scaling does not always enhance thermoelectric properties, depending on conditions.

Abstract

Low dimensional materials provide the possibility of improved thermoelectric performance due to the additional length scale degree of freedom for engineering their electronic and thermal properties. As a result of suppressed phonon conduction, large improvements on the thermoelectric figure of merit, ZT, have been recently reported in nanostructures, compared to the raw materials' ZT values. In addition, low dimensionality can improve a device's power factor, offering an additional enhancement in ZT. In this work the atomistic sp3d5s*-spin-orbit-coupled tight-binding model is used to calculate the electronic structure of silicon nanowires (NWs). The Landauer formalism is applied to calculate an upper limit for the electrical conductivity, the Seebeck coefficient, and the power factor. We examine n-type and p-type nanowires of diameters from 3nm to 12nm, in [100], [110], and [111] transport orientations at different doping concentrations. Using experimental values for the lattice thermal conductivity in nanowires, an upper limit for ZT is computed. We find that at room temperature, scaling the diameter below 7nm can at most double the power factor and enhance ZT. In some cases, however, scaling does not enhance the performance at all. Orientations, geometries, and subband engineering techniques for optimized designs are discussed.