Low Power Shift and Add Multiplier Design

TL;DR

This paper proposes a low power, low area shift-and-add multiplier architecture that reduces power consumption by over 35% and area by over 52% for 8-bit multipliers, with greater savings at higher bit widths.

Contribution

A novel low power, low area multiplier design that reduces switching activity and eliminates shifting, outperforming conventional architectures in power and area efficiency.

Findings

Power consumption reduced by 35.25% for 8-bit multipliers

Area reduced by 52.72% for 8-bit multipliers

Power savings increase with higher bit widths

Abstract

Today every circuit has to face the power consumption issue for both portable device aiming at large battery life and high end circuits avoiding cooling packages and reliability issues that are too complex. It is generally accepted that during logic synthesis power tracks well with area. This means that a larger design will generally consume more power. The multiplier is an important kernel of digital signal processors. Because of the circuit complexity, the power consumption and area are the two important design considerations of the multiplier. In this paper a low power low area architecture for the shift and add multiplier is proposed. For getting the low power low area architecture, the modifications made to the conventional architecture consist of the reduction in switching activities of the major blocks of the multiplier, which includes the reduction in switching activity of the adder and counter. This architecture avoids the shifting of the multiplier register. The simulation result for 8 bit multipliers shows that the proposed low power architecture lowers the total power consumption by 35.25% and area by 52.72 % when compared to the conventional architecture. Also the reduction in power consumption increases with the increase in bit width.