Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines

TL;DR

This paper proposes a hybrid memristor-MOS CAM architecture that enhances density, power efficiency, and speed potential for future high-performance search engines by leveraging memristor technology.

Contribution

It introduces a novel memristor-MOS based CAM design that integrates memristors for improved density, power management, and compatibility with CMOS processes.

Findings

Increased packing density due to memristor integration

Reduced power dissipation through block disabling

Potential for speed improvements as technology matures

Abstract

Large-capacity Content Addressable Memory (CAM) is a key element in a wide variety of applications. The inevitable complexities of scaling MOS transistors introduce a major challenge in the realization of such systems. Convergence of disparate technologies, which are compatible with CMOS processing, may allow extension of Moore's Law for a few more years. This paper provides a new approach towards the design and modeling of Memristor (Memory resistor) based Content Addressable Memory (MCAM) using a combination of memristor MOS devices to form the core of a memory/compare logic cell that forms the building block of the CAM architecture. The non-volatile characteristic and the nanoscale geometry together with compatibility of the memristor with CMOS processing technology increases the packing density, provides for new approaches towards power management through disabling CAM blocks without loss of stored data, reduces power dissipation, and has scope for speed improvement as the technology matures.