Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost

TL;DR

This paper introduces new cost metrics for reversible and quantum circuit synthesis, emphasizing physical constraints like Nearest Neighbor Cost (NNC), and discusses extending synthesis methods to optimize these metrics.

Contribution

It proposes cost metrics beyond traditional gate count and quantum cost, including NNC, and explores how to adapt synthesis flows to optimize these metrics for realistic hardware.

Findings

Evaluation metrics vary with additional costs

NNC significantly impacts circuit optimization

Extensions to synthesis flows can improve NNC while maintaining low quantum cost

Abstract

Many synthesis approaches for reversible and quantum logic have been proposed so far. However, most of them generate circuits with respect to simple metrics, i.e. gate count or quantum cost. On the other hand, to physically realize reversible and quantum hardware, additional constraints exist. In this paper, we describe cost metrics beyond gate count and quantum cost that should be considered while synthesizing reversible and quantum logic for the respective target technologies. We show that the evaluation of a synthesis approach may differ if additional costs are applied. In addition, a new cost metric, namely Nearest Neighbor Cost (NNC) which is imposed by realistic physical quantum architectures, is considered in detail. We discuss how existing synthesis flows can be extended to generate optimal circuits with respect to NNC while still keeping the quantum cost small.