Arithmetic Operations in Multi-Valued Logic

TL;DR

This paper develops and optimizes arithmetic operations in multi-valued logic systems, specifically Modulo-4 and Galois fields, with circuit designs and simulation results demonstrating their implementation.

Contribution

It introduces novel circuit designs for multi-valued logic arithmetic operations, including converters and optimized multipliers, with minimal gate usage and depth.

Findings

Successful implementation of arithmetic operations in MVL with reduced gate count.

Design of quaternary to binary converters using down literal circuits.

Simulation results validate the proposed circuit efficiencies.

Abstract

This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.