Design of A Low Power Low Voltage CMOS Opamp
Ratul Kr. Baruah (Tezpur University, India)

TL;DR
This paper presents a low power, low voltage CMOS operational amplifier operating at 2V and 1μA bias current, utilizing MOS transistors in moderate inversion to balance power and dynamic range, with improved performance over prior designs.
Contribution
The design introduces a novel biasing technique and transistor operation mode to achieve ultra-low power and voltage operation while maintaining high driving capability and small size.
Findings
Operates at 2V with 1μA bias current
Has a small area of 0.0084 mm² and high slew rate
Achieves lower power dissipation compared to existing opamps
Abstract
In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron…
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