Simulations of gated Si nanowires and 3-nm junctionless transistors

TL;DR

This paper uses first-principles simulations to demonstrate the feasibility of ultra-scaled junctionless silicon nanowire transistors at approximately 1 nm diameter and 3 nm gate length, emphasizing their potential as the primary design at these scales.

Contribution

It provides the first predictive simulations showing the physical viability of junctionless Si nanowire transistors at sub-2 nm dimensions, exploring atomic-level design factors.

Findings

Silicon nanowire transistors are feasible at ~1 nm diameter and ~3 nm gate length.

Junctionless design may be the only sensible option at these scales.

Atomic-level dopant placement significantly affects device performance.

Abstract

Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform predictive first-principles simulations of junctionless gated Si nanowire transistors. Our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of ~1 nm wire diameter and ~3 nm gate length, and that the junctionless transistor may be the only physically sensible design at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration.