Simulation of the Spin Field Effect Transistors: Effects of Tunneling and Spin Relaxation on its Performance

TL;DR

This paper presents a numerical simulation of spinFETs incorporating spin relaxation and tunneling effects, revealing more realistic performance limits and the impact of barrier design on magnetoresistance.

Contribution

It introduces a simulation method that includes both spin relaxation and tunneling effects, providing more accurate performance predictions for spinFETs.

Findings

Tunneling barriers increase magnetoresistance.

Spin relaxation reduces overall device performance.

Barrier design critically affects spinFET efficiency.

Abstract

A numerical simulation of spin-dependent quantum transport for a spin field effect transistor (spinFET) is implemented in a widely used simulator nanoMOS. This method includes the effect of both spin relaxation in the channel and the tunneling barrier between the source/drain and the channel. Account for these factors permits setting more realistic performance limits for the transistor, especially the magnetoresistance, which is found to be lower compared to earlier predictions. The interplay between tunneling and spin relaxation is elucidated by numerical simulation. Insertion of the tunneling barrier leads to an increased magnetoresistance. Numerical simulations are used to explore the tunneling barrier design issues.