Deep level transient spectroscopy study for the development of ion-implanted silicon field-effect transistors for spin-dependent transport

TL;DR

This study uses deep level transient spectroscopy to analyze defects in ion-implanted silicon transistors, optimizing annealing processes to improve dopant activation and device performance for spin-dependent transport applications.

Contribution

It provides a detailed DLTS analysis of implantation-induced defects and compares annealing strategies to enhance dopant activation and device quality.

Findings

950°C furnace anneal activates dopants but less effective in damage repair

1000°C rapid thermal anneal better repairs implantation damage

No bulk traps observed after annealing

Abstract

A deep level transient spectroscopy (DLTS) study of defects created by low-fluence, low-energy ion implantation for development of ion-implanted silicon field-effect transistors for spin-dependent transport experiments is presented. Standard annealing strategies are considered to activate the implanted dopants and repair the implantation damage in test metal-oxide-semiconductor (MOS) capacitors. Fixed oxide charge, interface trapped charge and the role of minority carriers in DLTS are investigated. A furnace anneal at 950 $\rm ^{o}$C was found to activate the dopants but did not repair the implantation damage as efficiently as a 1000 $\rm ^{o}$C rapid thermal anneal. No evidence of bulk traps was observed after either of these anneals. The ion- implanted spin-dependent transport device is shown to have expected characteristics using the processing strategy determined in this study.