Evaluation and Design Space Exploration of a Time-Division Multiplexed NoC on FPGA for Image Analysis Applications

TL;DR

This paper presents an adaptable FPGA-based Fat Tree NoC architecture optimized for image analysis applications, combining circuit and packet switching to efficiently handle high data bandwidth requirements.

Contribution

It introduces a novel, flexible NoC architecture tailored for image processing on FPGAs, integrating circuit and packet switching for improved data flow.

Findings

Supports high bandwidth data transfer for image analysis

Combines circuit-switching and packet-switching in NoC design

Uses reusable IP blocks for flexible architecture

Abstract

The aim of this paper is to present an adaptable Fat Tree NoC architecture for Field Programmable Gate Array (FPGA) designed for image analysis applications. Traditional NoCs (Network on Chip) are not optimal for dataflow applications with large amount of data. On the opposite, point to point communications are designed from the algorithm requirements but they are expensives in terms of resource and wire. We propose a dedicated communication architecture for image analysis algorithms. This communication mechanism is a generic NoC infrastructure dedicated to dataflow image processing applications, mixing circuit-switching and packet-switching communications. The complete architecture integrates two dedicated communication architectures and reusable IP blocks. Communications are based on the NoC concept to support the high bandwidth required for a large number and type of data.