Refinement and Verification of Real-Time Systems

TL;DR

This paper presents formal mechanisms for refining and verifying real-time systems within the ASTRAL language, enabling the systematic mapping of high-level specifications to lower-level parallel components while preserving timing and functional requirements.

Contribution

It introduces general refinement mechanisms for real-time systems in ASTRAL, allowing flexible implementation strategies with formal verification of timing and functional correctness.

Findings

Refinement mechanisms successfully applied to digital circuits and complex phone systems.

Design guidelines derived from practical specifications.

Formal verification ensures preservation of requirements during refinement.

Abstract

This paper discusses highly general mechanisms for specifying the refinement of a real-time system as a collection of lower level parallel components that preserve the timing and functional requirements of the upper level specification. These mechanisms are discussed in the context of ASTRAL, which is a formal specification language for real-time systems. Refinement is accomplished by mapping all of the elements of an upper level specification into lower level elements that may be split among several parallel components. In addition, actions that can occur in the upper level are mapped to actions of components operating at the lower level. This allows several types of implementation strategies to be specified in a natural way, while the price for generality (in terms of complexity) is paid only when necessary. The refinement mechanisms are first illustrated using a simple digital circuit; then, through a highly complex phone system; finally, design guidelines gleaned from these specifications are presented.