Performance Analysis of Software to Hardware Task Migration in Codesign

TL;DR

This paper models software-to-hardware task migration in multiprocessor systems on chip, using synchronous dataflow graphs to evaluate performance impacts and aid design decisions under complex multimedia application constraints.

Contribution

It introduces a modeling approach for software-to-hardware task migration using synchronous dataflow graphs to estimate performance impacts.

Findings

Model effectively predicts throughput changes due to migration.

Provides a framework for exploring design space solutions.

Assists in optimizing system performance under constraints.

Abstract

The complexity of multimedia applications in terms of intensity of computation and heterogeneity of treated data led the designers to embark them on multiprocessor systems on chip. The complexity of these systems on one hand and the expectations of the consumers on the other hand complicate the designers job to conceive and supply strong and successful systems in the shortest deadlines. They have to explore the different solutions of the design space and estimate their performances in order to deduce the solution that respects their design constraints. In this context, we propose the modeling of one of the design space possible solutions: the software to hardware task migration. This modeling exploits the synchronous dataflow graphs to take into account the different migration impacts and estimate their performances in terms of throughput.