VLSI Architectures for WIMAX Channel Decoders

TL;DR

This paper reviews various VLSI architectures for WiMax channel decoders, including convolutional, turbo, and LDPC codes, and presents a complete design for a convolutional turbo code encoder/decoder system.

Contribution

It provides a comprehensive overview of existing architectures and introduces a complete design for a convolutional turbo code system tailored for WiMax.

Findings

Reviewed main architectures for WiMax decoders

Presented a complete convolutional turbo code encoder/decoder design

Enhanced understanding of VLSI implementations for WiMax

Abstract

This chapter describes the main architectures proposed in the literature to implement the channel decoders required by the WiMax standard, namely convolutional codes, turbo codes (both block and convolutional) and LDPC. Then it shows a complete design of a convolutional turbo code encoder/decoder system for WiMax.